Due to the sensitive nature of CMOS integrated circuits (IC's), a concern with designing a CMOS IC is providing adequate protection of the IC from electrostatic discharges (ESD) that might damage the gate oxides and junctions of the IC. A countervailing consideration is that a device, termed a "voltage clamp," designed to protect the IC must not interfere with the operation of the IC under tolerated voltage conditions, yet must respond in such a way as to reliably protect the IC if such tolerated voltage conditions are exceeded.
FIG. 1 represents a schematic of a voltage clamp 10 that includes a metal gate field oxide (MGFO) transistor 12 and a parasitic NPN transistor 14. The MGFO and NPN transistors 12 and 14 are connected between an input pad 16 and a ground node of a CMOS IC 18. As shown, the MGFO transistor 12 is connected in the "OFF" state, i.e., with its gate and source grounded and its drain connected to the input pad 16. The NPN transistor 14 is also normally "OFF," with its emitter and base tied to ground and its collector tied to the input pad 16. The MGFO transistor 12 establishes the spacings and dimensions of the parasitic NPN transistor 14. With positive ESD voltages, the MGFO transistor 12 behaves as a parasitic NPN. With negative ESD voltages, the MGFO transistor 12 behaves as an NMOS transistor.
A cross-sectional representation is illustrated in FIG. 2A of a prior art voltage clamp 10a embodying the circuitry of FIG. 1. The voltage clamp 10a is formed in a silicon substrate 20 doped p-type, which is tied to ground 32 through a p-type region 36. Formed in the substrate 20 are an n-well 22, a field implant diffusion 24 doped p-type, a field oxide 28 overlying the field implant diffusion 24, and two regions 26 and 30 doped n-type, the latter of which is formed in the n-well 22. Finally, a metal gate electrode 34 tied to ground 32 overlies the field oxide 28 and contacts the first n-type region 26, while an input pad electrode 16a of a CMOS transistor (not shown) contacts the second n-type region 30. With this structure, an MGFO transistor is defined having a source region formed by the first n-type region 26, a drain region formed by the n-well 22, and a gate formed by the metal gate electrode 34, while an NPN transistor is defined having an emitter region also formed by the first n-type region 26, a collector region formed by the n-well 22, and a base region formed by the substrate 20 and the field implant diffusion 24. With the above, the first n-type region 26 (the MGFO source and the NPN emitter) is tied to ground 32, and the second n-type region 30 provides ohmic contact to the n-well 22 (the MGFO drain and NPN collector) for the input pad 16a.
The n-well 22 and the substrate 20 define an np junction 50 therebetween, and the field implant diffusion 24 increases the p-type carrier (hole) concentration in the field areas and thus raises the field threshold of the MGFO transistor and the collector-to-emitter breakdown voltage of the NPN transistor. Prior art layout practice dictates that the mask 38 for the field implant 40 (FIG. 2C) is laterally offset about 1.2 micrometers from the mask 42 for the n-well implant 44 (FIG. 2B), as seen by the placement of the field implant 40 relative to the n-well implant 44, the latter of which is shown in phantom in FIG. 2C. During diffusion of the n-well implant 44 to form the n-well 22, the concentration of electrons in the n-well 22 decreases as the junction 50 is approached. As a result, subsequent diffusion of the field implant 40 creates a lightly-doped region 50 at the np junction 50 between the field implant diffusion 24 and the n-well 22, as shown in FIG. 2A. The lightly-doped region is defined by that portion of the field implant diffusion 24 that overlaps the n-well 22 by no more than about 2 micrometers for the purpose of preventing premature breakdown of the np junction 50. If the voltage at the input pad 16a exceeds the collector-to-base breakdown voltage of the NPN transistor, the NPN transistor goes into an avalanche condition by which excess voltage at the input pad 16a is conducted and shunted through the substrate 20 to the first n-type region 26 and ground 32.
The suitability of a voltage clamp for a given application depends in part on the operating voltage of the IC to be protected. A particularly challenging application is CMOS IC's that operate at 12 volts dc (Vdc) off the battery supply of an automobile. Automobile battery voltages are defined herein as "high voltages" in order to be distinguished from "low voltage" automotive applications that operate at 5 Vdc and less. A complicating factor of high voltage applications is that automotive batteries have associated low-impedance transient voltages of about 40 Vdc (possibly higher transients are possible, but are less destructive due to a higher impedance), while the gate oxides for CMOS IC's used in these applications typically have rupture voltages of about 62 Vdc. Therefore, to prevent its destruction by low-impedance transients, a voltage clamp must tolerate certain transient voltages (e.g., about 40 Vdc), yet prevent higher voltages (e.g., about 62 Vdc) from reaching the CMOS IC. Prior art voltage clamps of the type shown in FIG. 2A exhibit collector-to-base breakdown voltages exceeding the gate oxide rupture voltage (about 62 Vdc) of CMOS devices operating at high voltages, and have therefore been unable to protect these devices.
Accordingly, what is needed is a voltage clamp that is reliably capable of protecting CMOS IC's employed in high voltage applications, such as IC's that operate at automotive battery voltages with 40 Vdc transients, without interfering with the operation of the IC at such voltages. Such a voltage clamp would preferably not entail processing that conflicts with or otherwise unduly complicates conventional processing employed to produce integrated circuits.